The bulk V nw of the programming transistor P w is optional it can be grounded or it can remain at the inhibiting voltage V N. The source region V p and the drain region D p of the cell's programming transistor P w are grounded. Then, an inhibiting voltage V N is applied to the bulk-connected source region V r of the cell's read transistor P r, to the commonly-connected drain, bulk and source regions V e of the cell's erase transistor P e, and to the drain region D r of the read transistor P r. 7,164,606, in accordance with the method of programming an NVM array that includes all-PMOS 4-transistor NVM cells having commonly-connected floating gates, for each cell 100 in the array that is to be programmed, all of the electrodes of the cell are grounded.
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